1. Field of the Invention
The present invention relates generally to a static-type semiconductor memory device. More specifically, the invention relates to a static-type semiconductor memory device employing a thin-film transistor as a load element of a memory cell.
2. Description of the Related Art
The conventional static-type semiconductor memory device has a memory cell portion which can be illustrated by an equivalent circuit shown in FIG. 5. Namely, a flip-flop forming the memory cell portion is formed by cross-connection of an inverter circuit, in which a P-channel type MOS transistor T1 and a N-channel type MOS transistor T2 are connected in series, and an inverter circuit, in which a P-channel type MOS transistor T3 and a N-channel type MOS transistor T4 are connected in series.
In the flip-flop, data of "1" or "0" can be arbitrarily stored in a storage node N1 between the P-channel type MOS transistor T1 and the N-channel type MOS transistor T2 and a storage node N2 between the P-channel type MOS transistor T3 and the N-channel type MOS transistor T4.
N-channel type MOS transistors T5 and T6 connected to respective storage nodes N1 and N2 form transfer gates for reading and writing operation from and to the corresponding one of the storage nodes. These N-channel type MOS transistor T5 and T6 are connected to a word line and bit lines. By appropriately selecting these word line and bit lines, arbitrary ones of the memory cells can be selected. Here, R3 and R4 denote resistor elements.
In recent years, in a high package density memory, such as a static-type semiconductor memory device having greater than or equal to 4 Mbits of memory capacity, P-channel type MOS transistors T1 and T3 are formed with thin film transistors (TFT) and arranged in the upper layer of the N-channel type MOS transistors T2 and T4. Such technology is described in "Starting of 4 Mbits SRAM Manufacturing" (Nikkei Micro-Device, June, 1991, Vol. 72, pp 35 to 62).
Namely, as shown in FIG. 6, N.sup.+ type diffusion layers (impurity doped region) 1 to 3 selectively formed on the surface of a semiconductor substrate of silicon form source and drain regions of the N-channel type MOS transistors T4 and T6, and N.sup.+ type diffusion layers 4 to 6 are source and drain regions of the N-channel type MOS transistors T2 and T5.
Reference numeral 7 denotes a gate electrode of the N-channel type MOS transistor T4 formed with a polycrystalline silicon layer (first polycrystalline silicon layer), and reference numeral 8 denotes a gate electrode of the N-channel type MOS transistor T2 formed with a polycrystalline silicon layer (first polycrystalline silicon layer).
Reference numerals 9, 10 denote word lines formed with the polycrystalline silicon layer (first polycrystalline silicon layer), which also serve as gate electrodes of the N-channel type MOS transistors T5 and T6. Reference numerals 11 and 12 denote grounding wiring (GND) of the N-channel type MOS transistors T2 and T4 formed with polycrystalline silicon layers (second polycrystalline silicon layer).
Reference numerals 24 and 25 denote TFT gate electrodes of the P-channel type MOS transistors T1 and T3 formed with the polycrystalline silicon layers (third polycrystalline silicon layer). Reference numerals 15 and 16 denote polycrystalline silicon layers (fourth polycrystalline silicon layer) serving as source and drain channel regions of the P-channel type MOS transistors T1 and T3 and also serving as Vcc wiring.
Reference numerals 17 and 18 denote through holes for connecting the N.sup.+ diffusion layer and the grounding wiring, 19 and 20 denote through holes for simultaneously connecting the gate electrode, the TFT gate electrode and the N.sup.+ diffusion layer, and 21 and 22 denote through holes connecting the TFT electrode and the TFT drain region.
In the N.sup.+ diffusion layers 1 and 4, through holes (not shown) for connecting bit lines (not shown) are opened. With the construction set forth above, the memory cell on the surface of the semiconductor substrate is realized.
On the other hand, the thin film transistor arranged in the upper layer of the N-channel type MOS transistor T2 comprises TFT gate electrode 25 (third polycrystalline silicon layer), and the polycrystalline silicon layer (fourth polycrystalline silicon layer) forming the source, drain and channel regions of the P-channel type MOS transistor T1, as shown in FIGS. 7 and 8.
A P.sup.+ implanting region 16a of the polcrystalline silicon layer 16 is a source region which also serves as the Vcc wiring. In the P.sup.+ implanting region 16a, a high concentration P-type impurity (P.sup.+) is implanted. A P.sup.- implanted region 16b and a P.sup.+ implanted region 16c are drain regions. In the P.sup.- implanted region 16b, low concentration P-type impurity (P.sup.-) is implanted, and in the P.sup.+ implanted region 16c, high concentration P-type impurity (P.sup.+) is implanted interfacing with the P.sup.- implanted region 16b. Here, 16d denotes a channel region.
Reference numeral 23 denotes an insulation layer disposed between the TFT gate electrode 25 and the polycrystalline silicon layer 16. With the construction set forth above, the thin film transistor is formed.
In the static-type semiconductor memory device as described above, there are problems in that a soft error can reverse stored data due to .alpha. ray generated from the package, the wiring material or so forth.
As a measure for such a soft error, there has been proposed a method to provide resistor elements R3 and R4 which are interposed between the P-channel type MOS transistor T1 and the N-channel type MOS transistor T2 and between the P-channel type MOS transistor T3 and the N-channel type MOS transistor T4, and to make the resistor elements R3 and R4 of a high resistance.
Such technology has been recorded in Ueda, Sasaki, Ishibashi, Yamanaka, "Improvement of Soft Error Immunity in a Polysilicon PMOS Load Memory Cell", Japanese Electronics and Communication Association, Autumn Meeting, 1991, Paper C-427, pp 5-141, which reports that providing high resistances for the resistor elements R3 and R4, resistance against the soft error can be improved.
Higher resistivity of the resistor elements R3 and R4 can be achieved by providing higher resistance for sheet resistance of the TFT gate electrodes 24 and 26. Since typically 1.times.10.sup.19 to 1.times.10.sup.29 atoms/cm.sup.3 of phosphorous ion is introduced in the TFT gate electrodes 24, 25, higher resistivity can be achieved by reducing the introduction amount of the phosphorous ion to 1.times.10.sup.17 to 1.times.10.sup.19.
Discussion will be given for the soft error with reference to FIG. 5. In FIG. 5, it is assumed that respective data "1" and "0" are stored in the storage nodes N1 and N2. When .alpha. ray generated from the package and so forth hits the storage node N1, the charge stored in the storage node N1 is withdrawn to reverse the content of the storage node N1 from "1" to "0".
Accordingly, the P-channel type MOS transistor T3 and the N-channel type MOS transistor T4 taking the potential of the storage node N1 as gate input are respectively turned ON and OFF. As a result, the content of the storage node N2 is reversed from "0" to "1". Therefore, the data stored in the memory cell is completely destroyed.
Here, when high resistance is provided for the resistor element R4, the transfer speed from the storage node N1 to the TFT gate electrode of the P-channel type MOS transistor T3 is reduced significantly to make the P-channel type MOS transistor T3 difficult to turn ON. As a result, reversal of the storage node N2 from "0" to "1" can be prevented.
Also, since the content of the storage node N2 is held "0", the storage node N1 which is once reversed can be re-charged by the P-channel type MOS transistor T1 to be restored from "0" to "1".
Therefore, even when .alpha. ray hits the storage node of the memory cell, the stored data in the memory cell cannot be destroyed. As set forth above, by providing higher resistance for the resistor elements R3 and R4, resistance against the software error can be improved.
Here, discussion will be given for the problem to provide high resistance for the resistor elements R3 and R4 and thus for the TFT gate electrodes. In a heat treatment step in the process of fabrication of the semiconductor device, it is possible that phosphorous ion introduced into the gate electrode (first polycrystalline silicon layer) is diffused to the TFT gate electrode through the through holes.
Namely, despite the reduction of the amount of phosphorous ion introduced into the TFT gate electrode for higher resistance, it is possible not to achieve high resistance of the TFT gate electrode since the phosphorous ion can be introduced into the gate electrode (first polycrystalline silicon layer) through the through hole.